【黑金教程笔记之006】【建模篇】【Lab 06 SOS信号之二】—笔记

 1 /****************************************
 2 module name: debounce_module.v
 3 function: debounce a key
 4 pin assignments(for DE2-115):
 5 
 6 
 7 by yf.x
 8 2014-11-05
 9 
10 ****************************************/
11 
12 module debounce_module(
13 CLK,
14 RST_n,
15 Pin_in,
16 Pin_out
17 );
18 
19 input CLK;
20 input RST_n;
21 input Pin_in;
22 output Pin_out;
23 
24 /*******************************/
25 
26 wire H2L_Sig;
27 wire L2H_Sig;
28 
29 detect_module u0(
30 .CLK(CLK),
31 .RST_n(RST_n),
32 .Pin_in(Pin_in),    //input from top
33 .H2L_Sig(H2L_Sig),  //output to u1
34 .L2H_Sig(L2H_Sig)   //output to u1
35 );
36 
37 /***************************************/
38 
39 delay_module u1(
40 .CLK(CLK),
41 .RST_n(RST_n),
42 .H2L_Sig(H2L_Sig),  //input from u1
43 .L2H_Sig(L2H_Sig),   //input from u1
44 .Pin_out(Pin_out)   //output to top
45 );
46 
47 /***************************************/
48 
49 endmodule

 1 /************************************************************
 2 module name: inter_control_module.v
 3 function: detect trig_sig and generate SOS_en_sig.
 4 
 5 by yf.x
 6 2014-11-08
 7 
 8 ************************************************************/
 9 
10 module inter_control_module(
11 CLK,
12 RST_n,
13 Trig_sig,
14 SOS_en_sig
15 );
16 
17 input CLK;
18 input RST_n;
19 input Trig_sig;
20 output SOS_en_sig;
21 
22 /****************************************************/
23 
24 reg i;
25 reg isEn;
26 
27 always @(posedge CLK or negedge RST_n)
28 if(!RST_n)
29 begin
30   i<=1‘b0;
31   isEn<=1‘b0;
32 end
33 else
34   case(i)
35     1‘b0:
36      if(Trig_sig)
37      begin
38        isEn<=1‘b1;
39         i<=1‘b1;
40      end
41     
42     1‘b1:
43      begin 
44        isEn<=1‘b0;
45        i<=1‘b0;
46      end
47   endcase
48 
49 /**********************************************************/
50 
51 assign SOS_en_sig=isEn;
52 
53 /**********************************************************/
54 
55 endmodule
56   
57           

  1 /**********************************************************
  2 module name:sos_module.v
  3 function: generate sos signal
  4 
  5 by yf.x
  6 2014-11-07
  7 
  8 **********************************************************/
  9 
 10 module sos_module(
 11 CLK,
 12 RST_n,
 13 Pin_out,
 14 SOS_en_sig
 15 );
 16 
 17 input CLK;
 18 input RST_n;
 19 input SOS_en_sig;
 20 output Pin_out;
 21 
 22 /***********************************************************/
 23 // DE2-115 use 50MHz oscillator,50M*0.001-1=49_999
 24 parameter T1ms=16‘d49_999;
 25 
 26 /**********************************************************/
 27 
 28 reg [15:0]count1; //1ms counter
 29 
 30 always @(posedge CLK or negedge RST_n)
 31 if(!RST_n)
 32   count1<=16‘d0;
 33 else if(iscount && count1==T1ms)
 34   count1<=16‘d0;
 35 else if(iscount)
 36   count1<=count1+1‘b1;
 37 else if(!iscount)  
 38   count1<=16‘d0;
 39   
 40 /***********************************************************/
 41 
 42 reg [9:0]count_ms;
 43 
 44 always @(posedge CLK or negedge RST_n)
 45 if(!RST_n)
 46   count_ms<=10‘d0;
 47 else if(iscount && count1==T1ms)
 48   count_ms<=count_ms+1‘b1;
 49 else if(!iscount)
 50   count_ms<=10‘d0;
 51 
 52 /***********************************************************/
 53 
 54 reg iscount;
 55 reg rPin_out;
 56 reg [4:0]i;  
 57 
 58 always @(posedge CLK or negedge RST_n)
 59 if(!RST_n)
 60 begin
 61   iscount<=1‘b0;
 62   rPin_out<=1‘b0;
 63   i<=5‘d0;
 64 end
 65 else
 66   case(i)
 67   
 68     5‘d0:
 69      if(SOS_en_sig==1‘b1)
 70        i<=5‘d1;
 71         
 72      5‘d1,
 73      5‘d3,
 74      5‘d5,
 75      5‘d13,
 76      5‘d15,
 77      5‘d17:       //short
 78      if(count_ms==10‘d100)
 79      begin
 80        iscount<=1‘b0;
 81         rPin_out<=1‘b0;
 82         i<=i+1‘b1;
 83      end
 84      else
 85      begin
 86        iscount<=1‘b1;
 87        rPin_out=1‘b1;
 88      end
 89     
 90     5‘d2,
 91      5‘d4,
 92      5‘d6,
 93      5‘d8,
 94      5‘d10,
 95      5‘d12,
 96      5‘d14,
 97      5‘d16,
 98      5‘d18:      //interval
 99      if(count_ms==10‘d50)
100     begin
101       iscount<=1‘b0;
102       i<=i+1‘b1;
103     end
104     else
105       iscount<=1‘b1;
106 
107     5‘d7,
108      5‘d9,
109      5‘d11:  //long
110     if(count_ms==10‘d300)
111     begin
112       iscount<=1‘b0;
113         rPin_out<=1‘b0;
114         i<=i+1‘b1;
115      end
116      else
117      begin
118        iscount<=1‘b1;
119        rPin_out=1‘b1;
120      end     
121      
122      5‘d19:  //end
123      begin
124        rPin_out<=1‘b0;
125         i<=1‘b0;
126      end
127     endcase
128     
129 /*******************************************************************/
130 
131 assign Pin_out=rPin_out;
132 
133 endmodule
134     
135     
136      
137       
138   

 1 /***********************************************************
 2 module name: lab06_top.v
 3 function: press a key, then trig SOS signal
 4 pin assignments(for DE2_115):
 5 ---------------------------------------------
 6 CLK--------------------------------CLOCK_50
 7 RST_n------------------------------KEY[0]
 8 Pin_in-----------------------------KEY[3]
 9 Pin_out----------------------------LEDG[8]
10 
11 by yf.x
12 2014-11-08
13 
14 ***********************************************************/
15 
16 module lab06_top(
17 CLK,
18 RST_n,
19 Pin_in,
20 Pin_out
21 );
22 
23 input CLK;
24 input RST_n;
25 input Pin_in;
26 output Pin_out;
27 
28 /**************************************************/
29 
30 wire Trig_sig;
31 
32 debounce_module u0(
33 .CLK(CLK),
34 .RST_n(RST_n),
35 .Pin_in(Pin_in),
36 .Pin_out(Trig_sig)
37 );
38 
39 /**************************************************/
40 
41 wire SOS_en_sig;
42 
43 inter_control_module u1(
44 .CLK(CLK),
45 .RST_n(RST_n),
46 .Trig_sig(Trig_sig),
47 .SOS_en_sig(SOS_en_sig)
48 );
49 
50 /***************************************************/
51 
52 sos_module u2(
53 .CLK(CLK),
54 .RST_n(RST_n),
55 .Pin_out(Pin_out),
56 .SOS_en_sig(SOS_en_sig)
57 );
58 
59 /***************************************************/
60 
61 endmodule