Answers For HDLbits - Verilog Language_Procedures

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
	assign out_assign = a & b;
	always @(*)
        out_alwaysblock = a & b ;
endmodule

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
	assign out_assign = a ^ b;
    always@(*) 
        out_always_comb = a ^ b;
    always@(posedge clk) 
        out_always_ff <= a ^ b;
endmodule

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    
    assign out_assign = sel_b1? sel_b2? b:a :a;

    always@(*)
        if(sel_b1&sel_b2)
            out_always = b;
        else
            out_always = a;
endmodule