cpu设计-->verilog理解

 1 module bjq (    input A,        //定义输入端口A
 2 
 3          input B,        //定义输入端口B
 4 
 5          output Sum,    //定义和输出端口Sum
 6 
 7          output Cout    //定义进位输出端口Cout
 8 
 9         ) ;
10 
11 wire  S1,T1;            //定义连接导线
12 
13 assign  Cout =T1;        //进位导线连接
14 
15 assign  Sum = S1;        //本位和导线连接
16 
17 yu yu1 (A, B, T1) ;        //连接调用逻辑与模块
18 
19 yihuo yihuo1(A,B,S1);    //连接调用逻辑异或模块
20 
21 endmodule

 1 parameter  MON=0,TUE=1,WED=2,THU=3,FRI=4,SAT=5,SUN=6;
 2 
 3 reg  [0:2]  Day;
 4 
 5 integer  Pocket_Money;
 6 
 7 case  (Day)
 8 
 9 TUE:  Pocket_Money=6;           //分支1
10 
11 MON,WED:   Pocket_Money=2;    //分支2
12 
13 FRI,SAT,SUN: Pocket_Money=7;        //分支3
14 
15 default:  Pocket_Money=0;             //分支4
16 
17 endcase