Verilog经典输入控制/激励信号模板1

reg [3:0]i; 
    
       always @ ( posedge CLOCK or negedge RESET ) 
           if( !RESET ) 
               begin 
                   i <= 4‘d0; 
                   Start_Sig <= 1‘b0; 
                   WrData <= 8‘d0; 
               end              
             else  
                 case( i ) 
                    
                        0:  
                        if( Done_Sig ) begin Start_Sig <= 1‘b0; i <= i + 1‘b1; end 
                        else begin WrData <= 8‘d8; Start_Sig <= 1‘b1; end 
                         
                        1: 
                        if( Done_Sig ) begin Start_Sig <= 1‘b0; i <= i + 1‘b1; end 
                        else begin WrData <= 8‘d9; Start_Sig <= 1‘b1; end 
                         
                        2: 
                        if( Done_Sig ) begin Start_Sig <= 1‘b0; i <= i + 1‘b1; end 
                        else begin WrData <= 8‘d10; Start_Sig <= 1‘b1; end 
                         
                        3: 
                        begin i <= i; end 
                    
                  endcase