VHDL设计时参数定义的方法 例子

标签：

-- SPtb

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY ROMtb IS
    -- Component Declaration for the Unit Under Test (UUT)
         --GENERIC ( INIT_0 : bit_vector(15 downto 0) := X"0000" );
         PORT (
      DO : out std_logic;
     I0 : in std_logic;
         I1 : in std_logic;
     I2 : in std_logic;
     I3 : in std_logic
         );
END ROMtb;
 
ARCHITECTURE behavior OF ROMtb IS
    COMPONENT ROM16
         GENERIC ( INIT_0 : bit_vector(15 downto 0) := X"0000" );
         PORT (
      DO : out std_logic;
     I0 : in std_logic;
         I1 : in std_logic;
     I2 : in std_logic;
     I3 : in std_logic
         );
    END COMPONENT;

BEGIN

    uut: ROM16 GENERIC MAP (INIT_0 => X"0000" )
                 PORT MAP (
                  DO => DO,
                  I0 => I0,
                  I1 => I1,
                  I2 => I2,
                  I3 => I3

        );

END;

VHDL设计时参数定义的方法 例子

标签：

原文地址：http://www.cnblogs.com/rednodel/p/4221382.html