标签:u-boot 移植 linux 2014.10 2440
硬件平台:tq2440
开发环境:Ubuntu-3.11
u-boot版本:2014.10
本文允许转载,请注明出处:http://blog.csdn.net/fulinus
在移植u-boot之前我们先熟悉一下硬件,以及如何控制硬件:
下面led.S是一位高人写的代码,完全是用ARM汇编编写的,短小精悍,主要是实现跑马灯的功能:
/*********************************************************************** * File: led.S * Version: 1.0.0 * Copyright: 2011 (c) Guo Wenxue <guowenxue@gmail.com> * Description: This ASM code used to turn LED0~LED4 on/off on TQ2440 board * ChangeLog: 1, Release initial version on "Sun Mar 20 18:41:04 CST 2011" * Modify: fulinux <fulinux@sina.com> ***********************************************************************/ #define GPBCON 0x56000010 #define GPBDAT 0x56000014 #define GPBUP 0x56000018 #define OUTPUT 0x01 /*Set GPIO port as output mode*/ #define INPUT 0x00 /*Set GPIO port as input mode*/ #define LED0 5 /*On TQ2440 board, LED0 use GPB5*/ #define LED1 6 /*On TQ2440 board, LED1 use GPB6*/ #define LED2 7 /*On TQ2440 board, LED2 use GPB7*/ #define LED3 8 /*On TQ2440 board, LED3 use GPB8*/ #define DELAY 0X1000000 .text .align 2 .global _start _start: /*Set GPB5,GPB6,GPB7,GPB8 as GPIO OUTPUT mode*/ ldr r0, =GPBCON ldr r1, [r0] bic r1, r1, #0x3FC00 /*Set GPBCON for GPB5,GPB6,GPB7,GPB8 as 0x00 */ orr r1, r1, #0x15400 /*Set GPBCON for GPB5,GPB6,GPB7,GPB8 as GPIOOUT, 0x01*/ str r1, [r0] /*Set internal pullup resister*/ ldr r0, =GPBUP ldr r1, [r0] orr r1, r1, #0x01E0 /*Set bit 5,6,7,8, disable pullup resister*/ @bic r1, r1, #0x01E0 /*Clear bit 5,6,7,8, enable pullup resister*/ str r1, [r0] loopled: /*Turn off LED0, LED1, LED2, LED3*/ ldr r2, =GPBDAT ldr r3, [r2] orr r3, r3, #0x01E0 /*Set bit 5,6,7,8 as high level*/ str r3, [r2] ldr r0, =DELAY /*Sleep for a while*/ bl delay /*Turn on LED0*/ ldr r3, [r2] bic r3, r3, #(1<<LED0) /*Clear bit 5, set GPB5 as low level*/ str r3, [r2] ldr r0, =DELAY /*Sleep for a while*/ bl delay /*Turn on LED1*/ ldr r3, [r2] bic r3, r3, #(1<<LED1) /*Clear bit 6, set GPB6 as low level*/ str r3, [r2] ldr r0, =DELAY /*Sleep for a while*/ bl delay /*Turn on LED2*/ ldr r3, [r2] bic r3, r3, #(1<<LED2) /*Clear bit 7, set GPB7 as low level*/ str r3, [r2] ldr r0, =DELAY /*Sleep for a while*/ bl delay /*Turn on LED3*/ ldr r3, [r2] bic r3, r3, #(1<<LED3) /*Clear bit 8, set GPB8 as low level*/ str r3, [r2] ldr r0, =DELAY /*Sleep for a while*/ bl delay b loopled /*Loop running LED*/ delay: sub r0, r0, #1 cmp r0, #0x0 bne delay mov pc, lr
# *********************************************************************** # * File: makefile # * Version: 1.0.0 # * Copyright: 2011 (c) Guo Wenxue <guowenxue@gmail.com> # * Description: Makefile used to cross compile the ASM and C source code # * ChangeLog: 1, Release initial version on "Mon Mar 21 21:09:52 CST 2011" # * # *********************************************************************** BINAME = led TEXTBASE = 0x33000000 CROSS = /opt/buildroot-2012.08/arm920t/usr/bin/arm-linux- CC = $(CROSS)gcc LD = $(CROSS)ld AR = $(CROSS)ar OBJCOPY = $(CROSS)objcopy OBJDUMP = $(CROSS)objdump STRIP = $(CROSS)strip READELF = $(CROSS)readelf CFLAGS = -g -O2 -Wall -nostdinc -nostdlib -fno-builtin AFLAGS = $(CFLAGS) -D__ASSEMBLY__ LDFLAGS = -Ttext $(TEXTBASE) SRC_C = $(wildcard *.c) SRC_S = $(wildcard *.S) OBJ_C = $(patsubst %.c,%.o,$(SRC_C)) OBJ_S = $(patsubst %.S,%.o,$(SRC_S)) OBJ_ALL = $(OBJ_C) $(OBJ_S) .PHONY : all all: ${OBJ_ALL} ${LD} $(LDFLAGS) -o ${BINAME}.elf ${OBJ_ALL} ${OBJCOPY} -O binary -S ${BINAME}.elf ${BINAME}.bin rm -f *.elf *.o %.o: %.S $(CC) $(AFLAGS) -c -o $@ $< %.o: %.c $(CC) $(CFLAGS) -c -o $@ $< install: cp ${BINAME}.bin ~/winxp -f --reply=yes clean: rm -f *.elf *.o rm -f ${BINAME}.bin
如图:
通过在命令行中键入如下命令:
h speed 12000 loadbin D:\kupan\temp\led.bin 0x33000000 setpc 0x33000000 g
这时你既可以看到4个led的跑马灯现象了!
讲下makefile中的几条语句:
SRC_C = $(wildcard *.c) SRC_S = $(wildcard *.S) OBJ_C = $(patsubst %.c,%.o,$(SRC_C)) OBJ_S = $(patsubst %.S,%.o,$(SRC_S)) OBJ_ALL = $(OBJ_C) $(OBJ_S)
OBJ_ALL = led.o
/******************************************************************************************** * File: bootstrap.S * Version: 1.0.0 * Copyright: 2011 (c) Guo Wenxue <Email: guowenxue@gmail.com QQ:281143292> * Description: If we wanna debug u-boot by J-Link in external SDRAM, we must download this * bootstrap.bin file into s3c24x0 8K internal SRAM(Stepping Stone) and excute * first, which used to initialize the CPU and external SDRAM. Only after init * the SDRAM then we can debug u-boot in it. * ChangeLog: 1, Release initial version on "Tue Jul 12 16:43:18 CST 2011" * *******************************************************************************************/ #include "bootstrap.h" .text .align 2 .global _start _start: /* set the cpu to SVC32 mode */ mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0xd3 msr cpsr, r0 /* Disable watchdog */ ldr r0, =S3C_WATCHDOG_BASE mov r1, #0 str r1, [r0] /* Disable Interrupt */ ldr r0, =S3C_INTERRUPT_BASE mov r1, #0xffffffff str r1, [r0, #INTMSK_OFFSET] ldr r1, =0x000007ff str r1, [r0, #INTSUBMSK_OFFSET] /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/Babjcgjg.html */ mov r0, #0 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache, Invalidate ICache and DCache */ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ /* disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) orr r0, r0, #0x00000002 @ set bit 2 (A) Align orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 /******************************************************************************************* * Init system clock and power, FCLK:HCLK:PCLK = 1:4:8 * Reference to S3C2440 datasheet: Chap 7 Clock&Power Management * * Initialize System Clock FCLK=400MHz HCLK=100MHz PCLK=50MHz * FCLK is used by ARM920T * HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, * the interrupt controller, the LCD controller, the DMA and USB host block. * PCLK is is used for APB bus,which is used by the peripherals such as WDT,IIS,I2C, * PWM timer,MMC interface,ADC,UART,GPIO,RTC and SPI. ******************************************************************************************/ /*Set LOCKTIME as default value 0x00ffffff*/ ldr r0, =S3C_CLOCK_POWER_BASE ldr r1, =0x00ffffff str r1, [r0, #LOCKTIME_OFFSET] /******************************************************************************************* * Reference to S3C2440 datasheet: Chap 7-8 ~ Page 242 * * Set the selection of Dividing Ratio between FCLK,HCLK and PCLK as FCLK:HCLK:PCLK = 1:4:8. * This ratio is determined by HDIVN(here is 2) and PDIVN(here is 1) control register. * Refer to the s3c2440 datasheet *******************************************************************************************/ ldr r0, =S3C_CLOCK_POWER_BASE mov r1, #5 str r1, [r0, #CLKDIVN_OFFSET] /*Set Clock Divider*/ mrc p15, 0, r1, c1, c0, 0 orr r1, r1, #0xc0000000 mcr p15, 0, r1, c1, c0, 0 /*************************************************************************************** * Reference to S3C2440 datasheet: Chap 7-20 ~ Page 254 * * Set MPLLCON(0x4C000004) register as: * [19:12]: MDIV(Main Divider control)=0x7F (value set in MDIV_405) * [9:4]: PDIV(Pre-devider control)=0x02 (value set in PSDIV_405) * [1:0]: SDIV(Post divider control)=0x01 (value set in PSDIV_405) * * MPLL(FCLK) = (2 * m * Fin)/(p * 2^s) * m=(MDIV+8), p=(PDIV+2), s=SDIV * * So FCLK=((2*(127+8)*Fin)) / ((2+2)*2^1) * = (2*135*12MHz)/8 * = 405MHz * For FCLK:HCLK:PCLK=1:4:8, so HCLK=100MHz, PCLK=50MHz ***************************************************************************************/ mov r1, #S3C_CLOCK_POWER_BASE mov r2, #MDIV_405 add r2, r2, #PSDIV_405 str r2, [r1, #MPLLCON_OFFSET] mem_init: /* memory control configuration */ /* make r0 relative the current location so that it */ /* reads SMRDATA out of FLASH rather than memory ! */ ldr r0, =SMRDATA ldr r1, =mem_init sub r0, r0, r1 adr r3, mem_init /* r3 <- current position of code */ add r0, r0, r3 /*r0 =SMRDATA-mem_init+mem_init =SMRDATA*/ ldr r1, =BWSCON /* Bus Width Status Controller */ add r2, r0, #13*4 0: ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne 0b /*Set GPIO5 OUTPUT mode*/ ldr r0, =GPBCON ldr r1, [r0] bic r1, r1, #0xC00 /*Set GPBCON for GPIO5 as 0x00 */ orr r1, r1, #0x0400 /*Set GPBCON for GPIO5 as GPIOOUT, 0x01*/ str r1, [r0] ldr r3, [r2] bic r3, r3, #(1<<LED0) /*Clear bit 5, set GPB5 as low level*/ str r3, [r2] /* everything is fine now */ dead_loop: b dead_loop .ltorg /* the literal pools origin */ SMRDATA: .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) .word 0xb2 .word 0x30 .word 0x30
[fulinux@ubuntu bootstrap]$ cat bootstrap.h /* * ===================================================================================== * * Filename: bootstrap.h * Version: 1.0.0 * Author: Guo Wenxue<Email: guowenxue@ghlsystems.com QQ:281143292> * CopyRight: 2011 (C) Guo Wenxue * Description: Some Reigster address definition for bootstrap.S * ===================================================================================== */ #define S3C_WATCHDOG_BASE 0x53000000 #define S3C_INTERRUPT_BASE 0x4a000000 #define SRCPND_OFFSET 0x00 #define INTMOD_OFFSET 0x04 #define INTMSK_OFFSET 0x08 #define PRIORITY_OFFSET 0x0c #define INTPND_OFFSET 0x10 #define INTOFFSET_OFFSET 0x14 #define SUBSRCPND_OFFSET 0x18 #define INTSUBMSK_OFFSET 0x1c #define S3C_CLOCK_POWER_BASE 0x4c000000 #define LOCKTIME_OFFSET 0x00 #define MPLLCON_OFFSET 0x04 #define UPLLCON_OFFSET 0x08 #define CLKCON_OFFSET 0x0c #define CLKSLOW_OFFSET 0x10 #define CLKDIVN_OFFSET 0x14 #define CAMDIVN_OFFSET 0x18 #define BWSCON 0x48000000 #define MDIV_405 0x7f << 12 #define PSDIV_405 0x21 #define GPBCON 0x56000010 #define GPBDAT 0x56000014 #define GPBUP 0x56000018 #define OUTPUT 0x01 /* Set GPIO port as output mode*/ #define INPUT 0x00 /* Set GPIO port as input mode*/ #define BEEP 0 /* On FL2440 board, LED0 use GPB0*/ #define LED0 5 /* On FL2440 board, LED0 use GPB5*/ #define LED1 6 /* On FL2440 board, LED0 use GPB6*/ #define LED2 8 /* On FL2440 board, LED0 use GPB8*/ #define LED3 10 /* On FL2440 board, LED0 use GPB10*/ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) #define DW32 (0x2) #define WAIT (0x1<<2) #define UBLB (0x1<<3) #define B1_BWSCON (DW16) #define B2_BWSCON (DW16) #define B3_BWSCON (DW16 + WAIT + UBLB) #define B4_BWSCON (DW16) #define B5_BWSCON (DW16) #define B6_BWSCON (DW32) #define B7_BWSCON (DW32) #define B0_Tacs 0x0 #define B0_Tcos 0x0 #define B0_Tacc 0x7 #define B0_Tcoh 0x0 #define B0_Tah 0x0 #define B0_Tacp 0x0 #define B0_PMC 0x0 #define B1_Tacs 0x0 #define B1_Tcos 0x0 #define B1_Tacc 0x7 #define B1_Tcoh 0x0 #define B1_Tah 0x0 #define B1_Tacp 0x0 #define B1_PMC 0x0 #define B2_Tacs 0x0 #define B2_Tcos 0x0 #define B2_Tacc 0x7 #define B2_Tcoh 0x0 #define B2_Tah 0x0 #define B2_Tacp 0x0 #define B2_PMC 0x0 #define B3_Tacs 0xc #define B3_Tcos 0x7 #define B3_Tacc 0xf #define B3_Tcoh 0x1 #define B3_Tah 0x0 #define B3_Tacp 0x0 #define B3_PMC 0x0 #define B4_Tacs 0x0 #define B4_Tcos 0x0 #define B4_Tacc 0x7 #define B4_Tcoh 0x0 #define B4_Tah 0x0 #define B4_Tacp 0x0 #define B4_PMC 0x0 #define B5_Tacs 0xc #define B5_Tcos 0x7 #define B5_Tacc 0xf #define B5_Tcoh 0x1 #define B5_Tah 0x0 #define B5_Tacp 0x0 #define B5_PMC 0x0 #define B6_MT 0x3 /* SDRAM */ #define B6_Trcd 0x1 #define B6_SCAN 0x1 /* 9bit */ #define B7_MT 0x3 /* SDRAM */ #define B7_Trcd 0x1 /* 3clk */ #define B7_SCAN 0x1 /* 9bit */ /* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ #define Trc 0x3 /* 7clk */ #define Tchr 0x2 /* 3clk */ #if defined(CONFIG_S3C2440) #define Trp 0x2 /* 4clk */ #define REFCNT 1012 #else #define Trp 0x0 /* 2clk */ #define REFCNT 0x0459 #endif
# *********************************************************************** # * File: makefile # * Version: 1.0.0 # * Copyright: 2011 (c) Guo Wenxue <guowenxue@gmail.com> # * Description: Makefile used to cross compile the ASM and C source code # * ChangeLog: 1, Release initial version on "Mon Mar 21 21:09:52 CST 2011" # * # *********************************************************************** BINAME = bootstrap TEXTBASE = 0 INST_PATH=${PWD}/../../../bin CROSS = arm-linux- CC = $(CROSS)gcc LD = $(CROSS)ld AR = $(CROSS)ar OBJCOPY = $(CROSS)objcopy OBJDUMP = $(CROSS)objdump STRIP = $(CROSS)strip READELF = $(CROSS)readelf CFLAGS = -g -O2 -Wall -nostdinc -nostdlib -fno-builtin AFLAGS = $(CFLAGS) -D__ASSEMBLY__ LDFLAGS = -Ttext $(TEXTBASE) SRC_C = $(wildcard *.c) SRC_S = $(wildcard *.S) OBJ_C = $(patsubst %.c,%.o,$(SRC_C)) OBJ_S = $(patsubst %.S,%.o,$(SRC_S)) OBJ_ALL = $(OBJ_C) $(OBJ_S) .PHONY : all all: ${OBJ_ALL} ${LD} $(LDFLAGS) -o ${BINAME}.elf ${OBJ_ALL} ${OBJCOPY} -O binary -S ${BINAME}.elf ${BINAME}.bin rm -f *.elf *.o make install %.o: %.S $(CC) $(AFLAGS) -c -o $@ $< %.o: %.c $(CC) $(CFLAGS) -c -o $@ $< install: cp -f ${BINAME}.bin ${INST_PATH} uninstall: rm -f ${INST_PATH}/${BINAME}.bin clean: rm -f *.elf *.o rm -f ${BINAME}.bin
u-boot-2014.10移植第3天----LED裸机程序
标签:u-boot 移植 linux 2014.10 2440
原文地址:http://blog.csdn.net/fulinus/article/details/40402235