AHB2reg接口转换

 1 assign mcu_xxx_addr = (rd_after_wr_reg || reg_valid_write_trans) ?
 2                  haddr_reg[ADDR_WIDTH+1:2] : haddr[ADDR_WIDTH+1:2];
 3 
 4 assign mcu_xx_rd_n = rd_after_wr ?  1‘b1 : rd_after_wr_reg ? 1‘b0 :       ~valid_read_trans;
 5 
 6 assign mcu_xxx_wr_n = ~(hready && reg_valid_write_trans);
 7 assign mcu_xxx_dat = hwdata;
 8 
 9 assign rd_after_wr = hready && valid_read_trans && reg_valid_write_trans;
10 
11 ----------------------------------------------------------------------------
12 assign hsize_error = BYTE_MASK ? ((hsize = SZ_DWORD) ||hsize[2]) :
13           (hsize != SZ_WORD);
14 assign valid_trans = hready && hsel && htrans[1] && !hsize_error;
15 assign error_trans = hready && hsel && htrans[1] && hsieze_error;
16 assign valid_read_trans = valid_trans && !hwrite;
17 assign  valid_write_trans = valid_trans && hwrite;
18 
19 always@(posedge hclk or negedge hresetn)
20   begin 
21      if(~hresetn)
22         begin 
23             rd_after_wr_reg = 1‘b0;
24          end
25       else
26           begin
27              id_after_wr_req <= rd_after_wr;
28           end
29     end
30 
31 
32 -------------------------------------------------------------------------------
33 always@(posedge hclk or negedge hresetn) 
34    begin 
35         if(~hresetn)
36           begin
37               haddr_reg <=0;
38               htrans_reg <= 0;
39               hwrite_reg <= 0;
40               hsize_reg <= 0;
41               reg_valid_read_trans <=0;
42               reg_valid_write_trans  <= 0;
43            end
44          else
45             begin
46                if(hready)
47                    begin 
48                       haddr_reg <= haddr;
49                       htrans_reg <= htrans;
50                       hwrite_reg <= hwrite;
51                       hsize_reg <= hsize;
52                       reg_valid_read_trans <=valid_read_trans;
53                       reg_valid_write_trans  <= valid_write_trans;
54                     end
55               end
56          end
57                        
58 
59 
60 --------------------------------------------------------------------------------
61   always@(*)
62      begin
63          if(hready && reg_valid_write_trans)
64             begin
65                 mcu_xxx_wr_en = 4‘b0;
66                 case(hsize_reg)
67                     SZ_BYTE:
68                       case(haddr_reg[1:0])
69                          2‘b00: mcu_xxx_wr_en[0] = 1‘b1;
70                          2‘‘b01: mcu_xxx_wr_en[1] = 1‘b1;
71                          2‘b10: mcu_xxxx_wr_en[2] = 1‘b1;
72                          2‘b11: mcu_xxx_wr_en [3]  = 1‘b1;
73                       endcase
74 
75                    SZ_HALF:
76                        case(haddr_reg[1])
77                            1‘b0 : mcu_xxx_wr_en[1:0] = 2‘b11;
78                            1‘b1 :  mcu_xxx_wr_en [3:2] = 2‘b11;
79                        endcase
80 
81                    SZ_WORD:
82                         mcu_xxx_wr_en = 4‘b1111;
83  
84                     default:
85                         mcu_xxx_wr_en = 4‘b1111;
86 
87                     endcase
88                end
89              else
90                  begin 
91                      mcu_xxx_wr_en = 4‘b0;
92                   end
93                end