how to forget about delta cycles for RTL design

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A delta cycle is a VHDL construct used to make
VHDL, a concurrent language, executable on a
sequential computer.

For RTL design, you can adopt some simple rules and
forget about delta cycles.

For testbenches, often you must have a good understanding
of what the simulator is doing.

The term "delta delay" refers to a signal being
scheduled a new value now, but the value does not get
applied until the next simulation cycle a delta cycle
later.

For RTL design, two simple rules:
1) All signal assignments in a clocked process (one that
describes a clock edge) create registers. Assignments in
a chain create a pipeline:

TwoRegProc : process
begin
wait until Clk = ‘1‘ ;
AReg1 <= A ;
AReg2 <= AReg1 ;
end process ;

2) In combinational logic, do not chain signal assignments
together in a process:
BadProc : process (A, B, C)
begin
Y <= A and B ;
X <= Y or C ;
end process ;

In this process, the value of Y seen by X is the
value form the previous execution. There are a number
of "ok" way to fix this, but the right way to do it is
to separate the logic into separate processes or concurrent
statements. In fact, in this case, two concurrent assignments
(ie: not in a process works best):

Y <= A and B ;
X <= Y or C ;

Remember those two points, and you can for the most part
forget about delta cycles for RTL design.

how to forget about delta cycles for RTL design

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原文地址：http://www.cnblogs.com/hfyfpga/p/4287497.html