VHDL之Port map and open

用的一些基本的库文件，有些端口自己不想用，恰巧好二哥(不知年龄的数字组组长，本名Holger)，于是请教之，告曰open关键词。后来深感自己VHDL水平太水，下了一本电子书恶补语法。明白了open，顺带了port mapping

<<Circuit Design With VHDL>> chapter 10, 10.4

现摘录如下，

Two ways to map the PORTS of a COMPONENT during its instantiation:

COMPONENT inverter IS
   PORT (a: IN STD_LOGIC; b: OUT STD_LOGIC);

END COMPONENT;

...

U1: inverter PORT MAP (x, y);

Positional mapping, that is, PORTS x and y correspond to a and b, respectively.

On the other hand, a nominal mapping would be the following:

U1: inverter PORT MAP (x=>a, y=>b);

Positional mapping is easier to write, but nominal mapping is less error-prone.

Ports can also be left unconnected (using the keyword OPEN). 

U2: my_circuit PORT MAP (x=>a, y=>b, w=>OPEN, z=>d);