交通信号灯

module jiaotong(clk,reset,lamp,downtime);
input clk,reset; 
output reg [5:0]lamp;
output[6:0]downtime;
reg [6:0]timedown;
reg[1:0]state;
reg [31:0]count1;

always@(clk)   //产生0~100s的计时
begin
  if(reset) count1<=0;        //计数器必须赋初值，否者无法进行计数
    else if(count1==32‘d100) count1<=0;
    else count1<=count1+1;
end

always@(clk or count1)
begin
if(reset) state<=0;
else if(count1>=32‘d1&&count1<=32‘d45)    state=0;
else if(count1>=32‘d46&&count1<=32‘d50)    state=1;
else if(count1>=32‘d51&&count1<=32‘d95)    state=2;
else if(count1>=32‘d96&&count1<=32‘d100)    state=3;
end

always@(clk)
begin    
    case(state)    //state只能在一个过程快内被赋值，所以其复位操作放在前一个always块中
    0:begin lamp<=6‘b100001; timedown<=‘d45-count1;end
    1:begin lamp<=6‘b010001; timedown<=‘d50-count1;end
    2:begin lamp<=6‘b001100; timedown<=‘d95-count1;end
    3:begin lamp<=6‘b001010; timedown<=‘d100-count1;end
    endcase
end

assign downtime=timedown;

endmodule

`timescale 1ms/1ms
`include "jiaotong.v"
module jiaotong_tp;
reg clk; reg reset;
wire [5:0]lamp;
wire [6:0]downtime;   //输出需用wire型
jiaotong u1(
            .clk(clk),
            .reset(reset),
            .lamp(lamp),
            .downtime(downtime)
            );
        
initial 
     begin   
     clk=0; reset=0;  
     #500 reset=1;
     #500 reset=0;   //需统一放入begin-end块中
     end 
     always #500  clk=~clk; 
     initial $monitor($time,,,"clk=%b count1=%d",clk,count1);  //只是在调试过程中监控count1的计数状态
  
   
endmodule