SRAM的读写操作

    /********************************Copyright**************************************                           
    **----------------------------File information--------------------------
    ** File name  : ZF_SRAM.v
    ** CreateDate :2014.11
    ** Funtions   : SRAM的读写功能,CS、LB、UB都被固定住(CS1 =L,CS2 =H,LB=L,UB=L)。读：WE =H,OE =L/写：we = L,OE = X;
                                    上电之后，先对SRAM 进行初始化，然后再写入读出。
                                    sram上半屏的数据地址：0- 5183（288*18），下半屏地址：5184 - 10367
    ** Operate on :M5C06N3L114C7
    ** Copyright  :All rights reserved. 
    ** Version    :V1.0
    **---------------------------Modify the file information----------------
    ** Modified by   :
    ** Modified data :        
    ** Modify Content:
    *******************************************************************************/
     

    module ZF_SRAM(
                                    clk_90m,
                                    rst_n,
                                    
                                    wr_reg,   //写数据使能
                                    rd_reg,   //读数据使能
                                    
                                    
                                    addr_wr_reg,  //写数据地址
                                    addr_rd_reg,  //读数据地址
                                    data_wr_reg,  //写操作数据寄存器
                                    data_rd_reg,  //读出的数据寄存器
                                    
                                    cs_sram,
                                    wr_sram,        //we
                                    rd_sram,        //oe
                                    addr_sram,
                                    data_sram_wr,    //写入的数据
                                    data_sram_rd,    //读入的数据
                                    dir_data,        //数据方向控制
                                    wr_over,
                                    rd_over,
                                    
                                    test_1,
                                    test_2
                                                                                                
                                        );

     parameter  width = 16;
        
    input               clk_90m;
    input               rst_n;

    input                wr_reg;        //写使能
    input                rd_reg;        //读使能


    input  [width -1:0]  addr_wr_reg;   //地址寄存器
    input  [width -1:0]  addr_rd_reg;   //地址寄存器
    input  [width -1:0]  data_wr_reg;   //待写数据寄存器
    output [width -1:0]  data_rd_reg;   //读出的数据寄存器
    reg    [width -1:0]  data_rd_reg_1;   //读出的数据寄存器


    output     reg       wr_sram;       //we
    output     reg       rd_sram;       //oe
    output     reg       cs_sram;

    output   reg  [width-1:0]   addr_sram;    //写出的信号
    output   reg  [width-1:0]   data_sram_wr; //写出的数据 
    input         [width-1:0]   data_sram_rd; //读入的数据
    output   reg                dir_data;     //数据方向的控制
    output   reg                wr_over;
    output   reg                rd_over;
    reg           [width-1:0]   data_zifu;
     output                     test_1;
     output                     test_2;
     
        //***************读写状态机**********************//
     parameter   idel_0 = 5‘d0;      //初始化显示界面
     parameter   idel_1 = 5‘d1;      //初始化显示界面2 
     parameter   idel_2 = 5‘d2;      //初始化显示界面
     parameter   idel_3 = 5‘d3;      //初始化显示界面2 
     parameter   idel_4 = 5‘d4;      //初始化显示界面 
     parameter   idel_5 = 5‘d5;      //初始化显示界面 
     
     parameter   idel = 5‘d6;
     parameter   wr_1 = 5‘d7;        //拉低cs
     parameter   wr_2 = 5‘d8;        //拉低wr
     parameter   wr_3 = 5‘d9;        //保持
     parameter   wr_4 = 5‘d10;        //拉高cs，wr
     parameter   wr_5 = 5‘d11;        //拉高结束
     parameter   wr_6 = 5‘d12;        //拉低结束
     parameter   wr_7 = 5‘d13;        //拉低结束
                         /* 留几个状态间隔 */
     
     parameter   rd_1 = 5‘d17;        //拉低cs
     parameter   rd_2 = 5‘d18;        //拉低rd 
     parameter   rd_3 = 5‘d19;        //保持 
     parameter   rd_4 = 5‘d20;        //拉高cs，rd 
     parameter   rd_5 = 5‘d21;        //拉高结束
     parameter   rd_6 = 5‘d22;        //拉低结束
   parameter   rd_7 = 5‘d23;        //拉低结束
     
     reg     [4:0]      state;
     reg     [15:0]     i;
     always @(posedge clk_90m or negedge rst_n)
     begin
        if(!rst_n)
         begin
                state <= idel_0;
                data_zifu <= 0;
                wr_sram <= 1;
                rd_sram <= 1; 
                cs_sram <= 1;
                addr_sram<= 0;
                data_sram_wr<= 0;
                dir_data <= 1;
                wr_over <= 0;
                rd_over <= 0;
                i <= 0;
            end
        else   
            begin
             case(state)    
                idel_0:
                     begin
                                wr_sram  <= 1;
                                rd_sram  <= 1; 
                                cs_sram  <= 1;
                                
                                addr_sram <= 0;
                                dir_data <= 1;
                                state <= idel_1;          
                            end
                idel_1:
                     begin
                            if(i >10 ) 
                                begin
                                        i <= 0;
                                        state <= idel;
                                end
                            else
                                    begin
                                         addr_sram <= i;    
                                         data_sram_wr <= 16‘h0000;
                                         state <= idel_2;
                                        end    
                         end
             idel_2:
                     begin     
                            cs_sram <= 0;    
                            state <= idel_3;                            
                         end
             idel_3:
                     begin        
                            state <= idel_4;         
                            wr_sram <= 0;     
                         end
             idel_4:
                     begin
                          state <= idel_5;         
                             wr_sram <= 0;                     
                        end
            idel_5 :
               begin
                        wr_sram <= 1;
                        cs_sram <= 1;    
                         i <= i + 1;
                        state <= idel_1;
                    end
        //----------------------------//
          /* 初始化完毕  */
                idel:
                    begin                        
                        wr_sram  <= 1;
                        rd_sram  <= 1; 
                        cs_sram  <= 1;
                        
                        addr_sram <= 0;
                        dir_data <= 0;
                        wr_over <= 0;
                        rd_over <= 0;    
                        if(wr_reg)     //写使能有效
                            begin
                                dir_data <= 1;     //写方向
                                addr_sram <= addr_wr_reg;  //寄存地址
                data_sram_wr <= data_wr_reg; //寄存写入的数据    
                                state <= wr_1;
                            end
                         else if(rd_reg)
                             begin
                                 dir_data <= 0;     //读方向     
                                 addr_sram <= addr_rd_reg;  //寄存地址
                                 state <= rd_1;     
                                end
                        else 
                            state <= idel;
                    end
             wr_1:
                 begin             
                        state <= wr_2;
                        cs_sram <= 0;    
                     end
             wr_2:
                 begin             
                     state <= wr_3;
                     wr_sram <= 0;    
                  end
                wr_3:
                 begin                                    
                     state <= wr_4;
                     wr_sram <= 0;    
                  end    
                wr_4:
                 begin                                     
                       state <= wr_5;
             cs_sram <= 1;    
                         wr_sram <= 1;    
                     end                     
                wr_5:
                    begin
                        wr_over <= 1;
                        state <= wr_6;
                    end
              wr_6:
                    begin
                        wr_over <= 0;
                        state <= idel;
                    end    
    
        //-------------------//            
                rd_1:
                    begin    
                             state <= rd_2;
                             cs_sram <= 0; 
                     end
                rd_2:
                    begin
                             state <= rd_3;
                             rd_sram <= 0;     
                     end
                rd_3:
                    begin
                         state <= rd_4;
                         rd_sram <= 0;     
                     end     
                rd_4:
                    begin
                         data_zifu <= data_sram_rd;  //读取数据        
                         state <= rd_5;
                         rd_sram <= 1; 
                         cs_sram <= 1;   
                     end                                       
                rd_5:
                     begin
                         rd_over <= 1;   
                         state <= rd_7;    
                     end
                rd_6:
                     begin
                         rd_over <= 0;    
                         state <= idel;    
                     end 
                default:state <= idel;
             endcase 
            end
        end
        

    always @(posedge clk_90m or negedge rst_n)
     begin
        if(!rst_n)
         begin
             data_rd_reg_1 <= 0;
            end
        else if(rd_over)
            begin
                data_rd_reg_1 <= data_zifu; 
             end
        else
                data_rd_reg_1 <= data_rd_reg_1;     
        end
        
   assign data_rd_reg = data_rd_reg_1;  
    //----------------------------
     assign  test_1 = wr_reg;
     assign  test_2 = data_sram_wr[7];
     
     
    endmodule