标签：des style blog http color 数据
The Direct I/O (Load/Store) module（即是LSU） serves as the source of all outgoing direct I/O packets（LSU用于配置发起数据读/写的SRIO设备端，发起端发送Direct IO包）. With direct I/O, the RapidIO packet contains the specific address where the data should be stored or read in the destination device. Direct I/O requires that a RapidIO source device keep a local table of addresses for memory within the destination device. Once these tables are established, the RapidIO source controller uses this data to compute the destination address and insert it into the packet header（将发起端想要访问的对端的地址插入包头中）.The RapidIO destination peripheral extracts the destination address from the received packet header and transfers the payload to memory via the DMA（对端SRIO设备从接收到的包头中提取目的地址（即发起端想要访问的对端内存的地址），然后对端SRIO通过DMA将包的payload传输到该目的地址）.When a CPU wants to send data from memory to an external processing element (PE) or read data from an external PE, it provides the RIO peripheral vital information about the transfer such asDSP memory address, target device ID, target destination address,packet priority, etc. Essentially, a means must exist to fill all the header fields of the RapidIO packet. The Load/Store module provides a mechanism to handle this information exchange via a set of MMRs acting as transfer descriptors. These registers,shown in Figure 2-8, are addressable by the CPU through the configuration bus（CPU可访问，这些寄存器就是LSU寄存器）. There are 8 LSU in total. Each LSU has its own set of 7-registers（有8组LSU寄存器，即SRIO同时可进行8个Direct IO传输，每组寄存器包括LSU_Reg0~7）. LSU_Reg0-4 is used to store “Control” information（LSU_Reg0-4包含用户配置的信息，即是控制信息）, LSU_reg5-6 for “Command” and Status information（LSU_reg5-6包含一些状态信息，反映了LSU寄存器的工作状态）. All these registers are RW except for LSU_REG6 which has a RO and a WO view. Upon completion of a write to LSUn_REG5, a data transfer is initiated for either an NREAD, NWRITE, NWRITE_R, SWRITE, ATOMIC, or MAINTENANCE RapidIO transaction（一旦完成写LSUn_REG5寄存器，SRIO硬件才真正启动工作，包括产生Direct IO包、发包等。n表示8组LSU寄存器索引）. Some fields, such as the RapidIO srcTID/targetTID field, are assigned by hardware and do not have a corresponding command register field.
LSU_Reg4寄存器中的ID Size（占2bit）：
8b表示DSP的SRIO设备ID用8bit表示，这样SRIO系统可以支持2^8个SRIO设备。
LSU_Reg4寄存器还可以配置包优先级、包从SRIO的哪个port传输出去、目的DSP的SRIO设备ID。
LSU_Reg5寄存器用于配置包类型（即操作类型）、doorbell的16bit信息等。
LSU_Reg3寄存器用于配置传输的字节数（可以分成多个包进行传输）、其中Drbll_val位的意思是：
当Drbll_val等于1的时候，表示LSU_Reg5中的16bit doorbell信息是有效的，然后会在最后一个数据包发送完毕后，才会发送doorbell包，该包的payload内容就是LSU_Reg5中的16bit doorbell信息，来通知（通过中断）对端SRIO发起端数据已操作完毕，对端可以做相应的处理。图中FType=10的包正是doorbell包，这里的Drbll_val位仅对非doorbell包有效，如NWRITE包，当通过NWRITE操作向对端写数据（通过NWRITE包）完毕后，会产生一个doorbell包通知对端，所以当配置NWRITE等操作时可以配置该位。
TI_DSP_SRIO - DirectIO操作-LSU,布布扣,bubuko.com
标签：des style blog http color 数据
原文地址：http://blog.csdn.net/yiyeguzhou100/article/details/36179387
