SAP computer之RAM

 1 library IEEE;
 2 use ieee.std_logic_1164.all;
 3 use ieee.numeric_std.all;
 4 
 5 entity ROM_16_8 is
 6 port
 7 (
 8     READ     : in     std_logic;                        --! Active low enable ROM signal, (tri-state)
 9     ADDRESS  : in     std_logic_vector (3 downto 0);    --! 4-bit ROM address bits from MAR
10     DATA_OUT : out    std_logic_vector (7 downto 0)     --! 8-bit ROM output word to W-bus
11 );        
12 end ROM_16_8 ;
13 
14 architecture beh of ROM_16_8 is
15 
16 type mem is array (0 to 15) of std_logic_vector(7 downto 0) ;
17 signal rom : mem;
18 
19 begin
20     --! This program works as follow:
21     --!
22     --! Load 5 to AC (memory content of 9)
23     --! Output 5 (content of AC)
24     --! Add 7 (memory content of 10) to 5 (AC content)
25     --! Output 12 (content of AC)
26     --! Add 3 (memory content of 11) to 12 (AC content)
27     --! Subtract 4 (memory content of 12) from 15 (AC content)
28     --! Output 11 (content of AC)
29     rom <= (
30             0 => "00001001" ,  -- LDA 9h ... Load AC with the content of memory location 9
31             1 => "11101111" ,  -- OUT
32             2 => "00011010" ,  -- ADD Ah ... Add the contents of memory location A to the AC content and replace the AC
33             3 => "11101111" ,  -- OUT
34             4 => "00011011" ,  -- ADD Bh ... Add the contents of memory location B to the AC content and replace the AC
35             5 => "00101100" ,  -- SUB Ch ... Sub the contents of memory location C from the AC content and replace the AC
36             6 => "11101111" ,  -- OUT
37             7 => "11111111" ,  -- HLT 
38             8 => "11111111" ,
39             9 => "00000101" ,   --5
40             10 => "00000111" ,  --7
41             11 => "00000011" ,  --3
42             12 => "00000100" ,  --4
43             13 => "11111111" , 
44             14 => "11111111" , 
45             15 => "11111111" );
46 
47     process (READ,ADDRESS)
48     begin
49         if READ = ‘0‘ then
50             DATA_OUT <= rom(to_integer(unsigned(ADDRESS))) ;
51          else
52              DATA_OUT <= (DATA_OUT‘range => ‘Z‘);
53         end if; 
54    end process ;
55    
56 end beh;