DE2之7-segment displays

 1 module SEG7_LUT    (    oSEG,iDIG    );
 2 input    [3:0]    iDIG;
 3 output    [6:0]    oSEG;
 4 reg        [6:0]    oSEG;
 5 
 6 always @(iDIG)
 7 begin
 8     case(iDIG)
 9     4‘h1: oSEG = 7‘b1111001;    // ---t----
10     4‘h2: oSEG = 7‘b0100100;     // |      |
11     4‘h3: oSEG = 7‘b0110000;     // lt     rt
12     4‘h4: oSEG = 7‘b0011001;     // |      |
13     4‘h5: oSEG = 7‘b0010010;     // ---m----
14     4‘h6: oSEG = 7‘b0000010;     // |      |
15     4‘h7: oSEG = 7‘b1111000;     // lb     rb
16     4‘h8: oSEG = 7‘b0000000;     // |      |
17     4‘h9: oSEG = 7‘b0011000;     // ---b----
18     4‘ha: oSEG = 7‘b0001000;
19     4‘hb: oSEG = 7‘b0000011;
20     4‘hc: oSEG = 7‘b1000110;
21     4‘hd: oSEG = 7‘b0100001;
22     4‘he: oSEG = 7‘b0000110;
23     4‘hf: oSEG = 7‘b0001110;
24     4‘h0: oSEG = 7‘b1000000;
25     endcase
26 end
27 
28 endmodule

 1 library IEEE;
 2 use ieee.std_logic_1164.all;
 3 
 4 --! 7-segment displays
 5 entity SEG7_LUT is 
 6 port
 7 (
 8   iDIG : in std_logic_vector(3 downto 0);
 9   oSEG : out std_logic_vector (6 downto 0)
10 );
11 end SEG7_LUT;
12 
13 architecture fpga of SEG7_LUT is
14 
15 begin
16 
17 pseg: process(iDIG)
18 begin
19   case iDIG is 
20     when "0001" =>
21       oSEG <= "1111001";
22     when "0010" =>
23       oSEG <= "0100100";
24     when "0011" =>
25       oSEG <= "0110000";
26     when "0100" =>
27       oSEG <= "0011001";
28     when "0101" =>
29       oSEG <= "0010010";
30     when "0110" =>
31       oSEG <= "0000010";
32     when "0111" =>
33       oSEG <= "1111000";
34     when "1000" =>
35       oSEG <= "0000000";
36     when "1001" =>
37       oSEG <= "0011000";
38     when "1010" =>
39       oSEG <= "0001000";
40     when "1011" =>
41       oSEG <= "0000011";
42     when "1100" =>
43       oSEG <= "1000110";
44     when "1101" =>
45       oSEG <= "0100001";
46     when "1110" =>
47       oSEG <= "0000110";
48     when "1111" =>
49       oSEG <= "0001110";
50     when "0000" => 
51       oSEG <= "1000000";
52      
53     end case;
54     
55 end process;
56 
57 end fpga;

 1 module SEG7_LUT_8 (oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
 2 input    [31:0]    iDIG;
 3 output    [6:0]    oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
 4 
 5 SEG7_LUT    u0    (    oSEG0,iDIG[3:0]        );
 6 SEG7_LUT    u1    (    oSEG1,iDIG[7:4]        );
 7 SEG7_LUT    u2    (    oSEG2,iDIG[11:8]    );
 8 SEG7_LUT    u3    (    oSEG3,iDIG[15:12]    );
 9 SEG7_LUT    u4    (    oSEG4,iDIG[19:16]    );
10 SEG7_LUT    u5    (    oSEG5,iDIG[23:20]    );
11 SEG7_LUT    u6    (    oSEG6,iDIG[27:24]    );
12 SEG7_LUT    u7    (    oSEG7,iDIG[31:28]    );
13 
14 endmodule

 1 library IEEE;
 2 use ieee.std_logic_1164.all;
 3 
 4 --! oSEG0 ~ oSEG7
 5 entity SEG7_LUT_8 is 
 6 port
 7 (
 8   iDIG  : in std_logic_vector(31 downto 0);
 9   oSEG0 : out std_logic_vector (6 downto 0);
10   oSEG1 : out std_logic_vector (6 downto 0);
11   oSEG2 : out std_logic_vector (6 downto 0);
12   oSEG3 : out std_logic_vector (6 downto 0);
13   oSEG4 : out std_logic_vector (6 downto 0);
14   oSEG5 : out std_logic_vector (6 downto 0);
15   oSEG6 : out std_logic_vector (6 downto 0);
16   oSEG7 : out std_logic_vector (6 downto 0)
17 );
18 end SEG7_LUT_8;
19 
20 --! architecture
21 architecture fpga of SEG7_LUT_8 is
22   
23 begin
24 
25 U0 : entity SEG7_LUT port map(oSEG => oSEG0,iDIG => iDIG(3 downto 0));
26 U1 : entity SEG7_LUT port map(oSEG => oSEG1,iDIG => iDIG(7 downto 4));
27 U2 : entity SEG7_LUT port map(oSEG => oSEG2,iDIG => iDIG(11 downto 8));
28 U3 : entity SEG7_LUT port map(oSEG => oSEG3,iDIG => iDIG(15 downto 12));
29 U4 : entity SEG7_LUT port map(oSEG => oSEG4,iDIG => iDIG(19 downto 16));
30 U5 : entity SEG7_LUT port map(oSEG => oSEG5,iDIG => iDIG(23 downto 20));
31 U6 : entity SEG7_LUT port map(oSEG => oSEG6,iDIG => iDIG(27 downto 24));
32 U7 : entity SEG7_LUT port map(oSEG => oSEG7,iDIG => iDIG(31 downto 28));
33 
34 end fpga;