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This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
1 std_logic_1164
1 PACKAGE std_logic_1164 IS 2 3 ------------------------------------------------------------------- 4 -- logic state system (unresolved) 5 ------------------------------------------------------------------- 6 TYPE std_ulogic IS ( ‘U‘, -- Uninitialized 7 ‘X‘, -- Forcing Unknown 8 ‘0‘, -- Forcing 0 9 ‘1‘, -- Forcing 1 10 ‘Z‘, -- High Impedance 11 ‘W‘, -- Weak Unknown 12 ‘L‘, -- Weak 0 13 ‘H‘, -- Weak 1 14 ‘-‘ -- Don‘t care 15 ); 16 -------------------------------------------------------------------------- 17 -- unconstrained array of std_ulogic for use with the resolution function 18 -------------------------------------------------------------------------- 19 TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; 20 21 ------------------------------------------------------------------- 22 -- resolution function 23 ------------------------------------------------------------------- 24 FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; 25 26 ------------------------------------------------------------------- 27 -- *** industry standard logic type *** 28 ------------------------------------------------------------------- 29 SUBTYPE std_logic IS resolved std_ulogic; 30 31 ----------------------------------------------------------------------- 32 -- unconstrained array of std_logic for use in declaring signal arrays 33 ----------------------------------------------------------------------- 34 TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; 35 36 ----------------------------------------------------------------------------- 37 -- common subtypes 38 ----------------------------------------------------------------------------- 39 SUBTYPE X01 IS resolved std_ulogic RANGE ‘X‘ TO ‘1‘; -- (‘X‘,‘0‘,‘1‘) 40 SUBTYPE X01Z IS resolved std_ulogic RANGE ‘X‘ TO ‘Z‘; -- (‘X‘,‘0‘,‘1‘,‘Z‘) 41 SUBTYPE UX01 IS resolved std_ulogic RANGE ‘U‘ TO ‘1‘; -- (‘U‘,‘X‘,‘0‘,‘1‘) 42 SUBTYPE UX01Z IS resolved std_ulogic RANGE ‘U‘ TO ‘Z‘; -- (‘U‘,‘X‘,‘0‘,‘1‘,‘Z‘) 43 44 ------------------------------------------------------------------- 45 -- overloaded logical operators 46 ------------------------------------------------------------------- 47 48 FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 49 FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 50 FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 51 FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 52 FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 53 function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01; 54 FUNCTION "not" ( l : std_ulogic ) RETURN UX01; 55 56 ----------------------------------------------------------------------- 57 -- vectorized overloaded logical operators 58 ----------------------------------------------------------------------- 59 FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; 60 FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 61 62 FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; 63 FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 64 65 FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; 66 FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 67 68 FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; 69 FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 70 71 FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; 72 FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 73 74 -- ----------------------------------------------------------------------- 75 -- Note : The declaration and implementation of the "xnor" function is 76 -- specifically commented until at which time the VHDL language has been 77 -- officially adopted as containing such a function. At such a point, 78 -- the following comments may be removed along with this notice without 79 -- further "official" ballotting of this std_logic_1164 package. It is 80 -- the intent of this effort to provide such a function once it becomes 81 -- available in the VHDL standard. 82 -- ----------------------------------------------------------------------- 83 function "xnor" ( l, r : std_logic_vector ) return std_logic_vector; 84 function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector; 85 86 FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; 87 FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector; 88 89 ------------------------------------------------------------------- 90 -- conversion functions 91 ------------------------------------------------------------------- 92 FUNCTION To_bit ( s : std_ulogic; xmap : BIT := ‘0‘) 93 RETURN BIT; 94 FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := ‘0‘) 95 RETURN BIT_VECTOR; 96 FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := ‘0‘) 97 RETURN BIT_VECTOR; 98 99 FUNCTION To_StdULogic (b : BIT ) RETURN std_ulogic; 100 FUNCTION To_StdLogicVector (b : BIT_VECTOR ) RETURN std_logic_vector; 101 FUNCTION To_StdLogicVector (s : std_ulogic_vector) RETURN std_logic_vector; 102 FUNCTION To_StdULogicVector(b : BIT_VECTOR ) RETURN std_ulogic_vector; 103 FUNCTION To_StdULogicVector(s : std_logic_vector) RETURN std_ulogic_vector; 104 105 ------------------------------------------------------------------- 106 -- strength strippers and type convertors 107 ------------------------------------------------------------------- 108 109 FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector; 110 FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; 111 FUNCTION To_X01 ( s : std_ulogic ) RETURN X01; 112 FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector; 113 FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; 114 FUNCTION To_X01 ( b : BIT ) RETURN X01; 115 116 FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector; 117 FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector; 118 FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z; 119 FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector; 120 FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector; 121 FUNCTION To_X01Z ( b : BIT ) RETURN X01Z; 122 123 FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector; 124 FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; 125 FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01; 126 FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector; 127 FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; 128 FUNCTION To_UX01 ( b : BIT ) RETURN UX01; 129 130 ------------------------------------------------------------------- 131 -- edge detection 132 ------------------------------------------------------------------- 133 FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; 134 FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; 135 136 ------------------------------------------------------------------- 137 -- object contains an unknown 138 ------------------------------------------------------------------- 139 FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN; 140 FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN; 141 FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN; 142 143 END std_logic_1164;
2 resolution function
1 function resolved ( s : std_ulogic_vector ) return std_ulogic; 2 variable result : std_ulogic := ‘Z‘; -- weakest state default 3 begin 4 -- the test for a single driver is essential otherwise the 5 -- loop would return ‘X‘ for a single driver of ‘-‘ and that 6 -- would conflict with the value of a single driver unresolved signal. 8 if s‘length = 1 then 9 return s(s‘low); 10 else 11 for i in s‘range loop 12 result := resolution_table(result, s(i)); 13 end loop; 14 end if; 15 return result; 16 end resolved; 17 18 19 constant resolution_table : stdlogic_table := ( 20 -- --------------------------------------------------------- 21 -- | U X 0 1 Z W L H - | | 22 -- --------------------------------------------------------- 23 ( ‘U‘, ‘U‘, ‘U‘, ‘U‘, ‘U‘, ‘U‘, ‘U‘, ‘U‘, ‘U‘ ), -- | U | 24 ( ‘U‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘ ), -- | X | 25 ( ‘U‘, ‘X‘, ‘0‘, ‘X‘, ‘0‘, ‘0‘, ‘0‘, ‘0‘, ‘X‘ ), -- | 0 | 26 ( ‘U‘, ‘X‘, ‘X‘, ‘1‘, ‘1‘, ‘1‘, ‘1‘, ‘1‘, ‘X‘ ), -- | 1 | 27 ( ‘U‘, ‘X‘, ‘0‘, ‘1‘, ‘Z‘, ‘W‘, ‘L‘, ‘H‘, ‘X‘ ), -- | Z | 28 ( ‘U‘, ‘X‘, ‘0‘, ‘1‘, ‘W‘, ‘W‘, ‘W‘, ‘W‘, ‘X‘ ), -- | W | 29 ( ‘U‘, ‘X‘, ‘0‘, ‘1‘, ‘L‘, ‘W‘, ‘L‘, ‘W‘, ‘X‘ ), -- | L | 30 ( ‘U‘, ‘X‘, ‘0‘, ‘1‘, ‘H‘, ‘W‘, ‘W‘, ‘H‘, ‘X‘ ), -- | H | 31 ( ‘U‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘, ‘X‘ ) -- | - | 32 );
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原文地址：http://www.cnblogs.com/mengdie/p/4597923.html
