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// 头文件//
module my_uart_top(
CLK,rst_n,rs232_rx,rd_fifo_ena,rd_fifo_data,
rs232_tx,wr_fifo_req,rd_fifo_req,wr_fifo_data,clk_bps_tx,clk_h
);
//Inputs
input CLK; // 50MHz?????
input rst_n; //??????λ???
input rs232_rx; // RS232???????????
input rd_fifo_ena;
input [7:0] rd_fifo_data;
//Outputs
output rs232_tx; // RS232???????????
output wr_fifo_req;
output rd_fifo_req;
output [7:0] wr_fifo_data;
output clk_bps_tx;
output clk_h;
wire clk_bps_rx;
wire clk_bps_tx;
wire bps_start_rx;
wire bps_start_tx;
wire rd_fifo_ena1;
wire [7:0] rd_fifo_data1; //??????????????????????????????
wire [7:0] cnt;
//wire rd_fifo_0 = (cnt>=6)? rd_fifo_req : 1‘b0;
wire clk_100MHz;
/////////////////////////////////////////////////////////////////////////////////////////
//------rx---------//
//
pll pll(
.inclk0(CLK),
.c0(clk),
.c1(clk_25M)
);
speed_select speed_rx( .clk(clk), //???????????飬??????????鸴?ã?????????????
.rst_n(rst_n),
.bps_start(bps_start_rx),
.clk_bps(clk_bps_rx)
);
my_uart_rx uart_rx( .clk(clk), //???????????
.rst_n(rst_n),
.rs232_rx(rs232_rx),
.clk_bps(clk_bps_rx),
.clk_h(clk_h),
.en_1(en_1),
.bps_start(bps_start_rx),
.wr_fifo_data(wr_fifo_data),
.wr_fifo_req(wr_fifo_req) //"1"
);
//wr_fifo fifo (
// .clock(clk),
// .data(wr_fifo_data),
// .rdreq(rd_fifo),
// .wrreq(wr_fifo_req),
// .empty(rd_fifo_ena1),
// .full(),
// .q(rd_fifo_data1),
// .usedw(cnt)
// );
//////////////////////////////////////////////////////////////////////////////////////////
//
speed_select speed_tx( .clk(clk), //???????????飬??????????鸴?ã?????????????
.rst_n(rst_n),
.bps_start(bps_start_tx),
.clk_bps(clk_bps_tx)
);
wire[7:0] wr_fifo_data;
wire en_1;
my_uart_tx uart_tx( .clk(clk), //???????????
.rst_n(rst_n),
.clk_bps(clk_bps_tx),
.rd_fifo_data(rd_fifo_data),
.rd_fifo_ena(rd_fifo_ena),
.wr_fifo_data(wr_fifo_data),
.en_1(en_1),
.rs232_tx(rs232_tx),
.bps_start(bps_start_tx),
.rd_fifo_req(rd_fifo_req)
);
wire rd_fifo_req;
zh_1 zh_1(
. clk(clk),
. rd_fifo_req(rd_fifo_req),
. wrfifo_1(wr_fifo_data)
//. chu_1(chu_1)
);
zh_2 zh_2(
.clk(clk),
. wrfifo_1(wr_fifo_data),
. rd_fifo_req(rd_fifo_req),
.clk_25M(clk_25M)
);
endmodule
// 速度选择 //
module speed_select(clk,rst_n,bps_start,clk_bps);
input clk; //50MHz?????
input rst_n; //??????λ???
input bps_start; //????????????????????????????λ
output clk_bps; // clk_bps????????????????????λ???м???????
parameter BPS9600 = 5207, //???????9600bps
BPS19200 = 2603, //???????19200bps
BPS38400 = 2603, //???????38400bps BPS38400 = 1301,
BPS57600 = 867, //???????57600bps
BPS115200 = 433; //???????115200bps
parameter BPS9600_2 = 2603,
BPS19200_2 = 1301,
BPS38400_2 = 1301, //650
BPS57600_2 = 433,
BPS115200_2 = 216;
parameter CLK_100M = 1000000,
BTF9600 = 96,
BTF19200 = 192,
BTF38400 = 384,
BTF57600 = 576,
BTF115200 = 1152;
reg[12:0] bps_para; //????????????
reg[12:0] bps_para_2; //????????????
reg[12:0] cnt; //???????
reg clk_bps_r; //?????????????
reg[31:0] clk_count;
//----------------------------------------------------------
reg[2:0] uart_ctrl; // uart??????????????
//----------------------------------------------------------
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
uart_ctrl <= 3‘d2; //?????????38400bps
else
case (uart_ctrl) //??????????
3‘d0: begin
bps_para <= BPS9600;
bps_para_2 <= BPS9600_2;
end
3‘d1: begin
bps_para <= BPS19200;
bps_para_2 <= BPS19200_2;
end
3‘d2: begin
bps_para <= BPS38400;
bps_para_2 <= BPS38400_2;
end
3‘d3: begin
bps_para <= BPS57600;
bps_para_2 <= BPS57600_2;
end
3‘d4: begin
bps_para <= BPS115200;
bps_para_2 <= BPS115200_2;
end
default: ;
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= 13‘d0;
else if(bps_start)
if(cnt==bps_para)
cnt <= 13‘d0;
else
cnt <= cnt + 1‘b1; //????????????????
else
cnt <= 13‘d0;
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
clk_bps_r <= 1‘b0;
else if(cnt==bps_para_2)// && bps_start)
clk_bps_r <= 1‘b1; // clk_bps_r???????????????????λ???м???????
else
clk_bps_r <= 1‘b0;
end
assign clk_bps = clk_bps_r;
endmodule
/*
input clk; //50MHz?????
input rst_n; //??????λ???
input bps_start; //????????????????????????????λ
output clk_bps; // clk_bps????????????????????λ???м???????
parameter BPS9600 = 5207, //???????9600bps
BPS19200 = 2603, //???????19200bps
BPS38400 = 2603, //???????38400bps BPS38400 = 1301,
BPS57600 = 867, //???????57600bps
BPS115200 = 433; //???????115200bps
parameter BPS9600_2 = 2603,
BPS19200_2 = 1301,
BPS38400_2 = 1301, //650
BPS57600_2 = 433,
BPS115200_2 = 216;
parameter CLK_100M = 1000000,
BTF9600 = 96,
BTF19200 = 192,
BTF38400 = 384,
BTF57600 = 576,
BTF115200 = 1152;
reg[12:0] bps_para; //????????????
reg[12:0] bps_para_2; //????????????
reg[12:0] cnt; //???????
reg clk_bps_r; //?????????????
reg[31:0] clk_count;
//----------------------------------------------------------
reg[2:0] uart_ctrl; // uart??????????????
//----------------------------------------------------------
//always @ (posedge clk or negedge rst_n)
//begin
// if(!rst_n)
// uart_ctrl <= 3‘d2; //?????????38400bps
// else
// case (uart_ctrl) //??????????
// 3‘d0: begin
// bps_para <= BPS9600;
// bps_para_2 <= BPS9600_2;
// end
// 3‘d1: begin
// bps_para <= BPS19200;
// bps_para_2 <= BPS19200_2;
// end
// 3‘d2: begin
// bps_para <= BPS38400;
// bps_para_2 <= BPS38400_2;
// end
// 3‘d3: begin
// bps_para <= BPS57600;
// bps_para_2 <= BPS57600_2;
// end
// 3‘d4: begin
// bps_para <= BPS115200;
// bps_para_2 <= BPS115200_2;
// end
// default: ;
// endcase
//end
//always @ (posedge clk or negedge rst_n)
//begin
// if(!rst_n)
// cnt <= 13‘d0;
// else if(bps_start)
// if(cnt==bps_para)
// cnt <= 13‘d0;
// else
// cnt <= cnt + 1‘b1; //????????????????
// else
// cnt <= 13‘d0;
//end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
uart_ctrl <= 3‘d4; //?????????38400bps
else
case (uart_ctrl) //??????????
3‘d0: begin
bps_para <= BTF9600;
end
3‘d1: begin
bps_para <= BTF19200;
end
3‘d2: begin
bps_para <= BTF38400;
end
3‘d3: begin
bps_para <= BTF57600;
end
3‘d4: begin
bps_para <= BTF115200;
end
default: ;
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
clk_count <= 32‘d0;
else if(bps_start)
if( clk_count >= CLK_100M )
begin
clk_count <= clk_count - CLK_100M + bps_para;
// clk_bps_r <= 1‘b0;
end
else if( clk_count >= CLK_100M / 2 )
begin
// clk_bps_r <= 1‘b1; // clk_bps_r???????????????????λ???м???????
clk_count <= clk_count + bps_para;
end
else
begin
clk_count <= clk_count + bps_para; //????????????????
// clk_bps_r <= 1‘b0;
end
else
clk_count <= 32‘d0;
end
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
clk_bps_r <= 1‘b0;
else if(clk_count >= CLK_100M / 2 )// && bps_start)
clk_bps_r <= 1‘b1; // clk_bps_r???????????????????λ???м???????
else
clk_bps_r <= 1‘b0;
end
//always @ (posedge clk or negedge rst_n)
//begin
// if(!rst_n)
// cnt <= 13‘d0;
// else if((cnt==bps_para) || (~bps_start))
// cnt <= 13‘d0;
// else
// cnt <= cnt + 1‘b1; //????????????????
//end
//always @ (posedge clk or negedge rst_n)
//begin
// if(!rst_n)
// clk_bps_r <= 1‘b0;
// else if(cnt==bps_para_2)// && bps_start)
// clk_bps_r <= 1‘b1; // clk_bps_r???????????????????λ???м???????
// else
// clk_bps_r <= 1‘b0;
//end
assign clk_bps = clk_bps_r;
endmodule
*/
// 发数据 //
module my_uart_rx(clk,rst_n,rs232_rx,clk_bps,bps_start,wr_fifo_data,wr_fifo_req,en_1,clk_h);
input clk;
input rst_n;
input rs232_rx;
input clk_bps;
output en_1;
output reg clk_h;
output bps_start;
output [7:0] wr_fifo_data;
output wr_fifo_req;
reg[31:0]cnt1;
parameter SEC_TIME=100;
always@(posedge clk)
if(cnt1 == SEC_TIME)
begin
cnt1 <= 32‘b0;
clk_h = !clk_h;
end
else cnt1 <= cnt1 + 1‘b1;
reg clk_bps_reg0;
reg clk_bps_reg1;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
clk_bps_reg0 <= 1‘b0;
clk_bps_reg1 <= 1‘b0;
end
else
begin
clk_bps_reg0 <= clk_bps;
clk_bps_reg1 <= clk_bps_reg0;
end
end
reg rs232_rx_reg0,rs232_rx_reg1;
wire neg_rs232_rx;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rs232_rx_reg0 <= 1‘b0;
rs232_rx_reg1 <= 1‘b0;
end
else
begin
//en_1<=bps_start;
rs232_rx_reg0 <= rs232_rx;
rs232_rx_reg1 <= rs232_rx_reg0;
end
end
assign neg_rs232_rx = rs232_rx_reg1 && ~rs232_rx_reg0;
reg bps_start;
reg wr_fifo_req;
reg rx_int;
reg [3:0] num;
reg rs232_start;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
//en_1<=1‘b0;
rx_int <= 1‘b0;
bps_start <= 1‘b0;
wr_fifo_req <= 1‘b0;
// en_1<=1‘b0;
rs232_start <= 1‘b1;
rs232_start <= 1‘b0;
end
else if( ( neg_rs232_rx == 1‘b1 ) && ( rs232_start == 1‘b0 ) ) //每发一次就进行一次
begin
rx_int <= 1‘b1;
bps_start <= 1‘b1;
wr_fifo_req <= 1‘b0;
end
else if(num==4‘d10)
begin
rs232_start <= 1‘b0;
rx_int <= 1‘b0;
bps_start <= 1‘b0;
wr_fifo_req <= 1‘b1;
en_1<=1‘b1;
end
else
begin
rx_int <= rx_int;
bps_start <= bps_start;
wr_fifo_req <= 1‘b0;
en_1<=1‘b0;
end
end
reg [7:0] rx_data_r;
reg [9:0] rx_temp_data;
reg [10:0] cnt;
reg en_1;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
// en_1<=1‘b0;
rx_temp_data <= 8‘d0;
num <= 4‘d0;
rx_data_r <= 8‘d0;
end
else if(rx_int)
begin //???????????
if( ( clk_bps == 1‘b1 ) && ( clk_bps_reg0 == 1‘b0 ) )//检测他的上升沿
begin //?????????????,???????????????λ??8bit????????????λ
num <= num + 1‘b1;
case(num)
4‘d0: rx_temp_data[0] <= rs232_rx; //???λ
4‘d1: rx_temp_data[1] <= rs232_rx; //0 bit
4‘d2: rx_temp_data[2] <= rs232_rx; //1 bit
4‘d3: rx_temp_data[3] <= rs232_rx; //2 bit
4‘d4: rx_temp_data[4] <= rs232_rx; //3 bit
4‘d5: rx_temp_data[5] <= rs232_rx; //4 bit
4‘d6: rx_temp_data[6] <= rs232_rx; //5 bit
4‘d7: rx_temp_data[7] <= rs232_rx; //6 bit
4‘d8: rx_temp_data[8] <= rs232_rx; //7 bit
4‘d9: rx_temp_data[9] <= rs232_rx; //????λ
default:;
endcase
end
else if(num==4‘d10)
begin
// en_1<=1‘b1;
num <= 4‘d0;
//?????STOPλ??????,num????
rx_data_r <= rx_temp_data[8:1]; //?????????浽????????rx_data??
end
// else en_1<=1‘b0;
end
end
assign wr_fifo_data = rx_data_r;
endmodule
// 收数据//
module my_uart_tx(clk,rst_n,clk_bps,rd_fifo_data,rd_fifo_ena,rs232_tx,bps_start,rd_fifo_req,wr_fifo_data,en_1);
input clk;
input rst_n;
input clk_bps;
input [7:0] rd_fifo_data;
input rd_fifo_ena;
input [7:0] wr_fifo_data;
input en_1;
output rs232_tx;
output bps_start;
output rd_fifo_req;
reg clk_bps_reg0;
reg clk_bps_reg1;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
clk_bps_reg0 <= 1‘b0;
clk_bps_reg1 <= 1‘b0;
end
else
begin
clk_bps_reg0 <= clk_bps;
clk_bps_reg1 <= clk_bps_reg0;
end
end
reg rd_fifo_ena_reg0;
reg rd_fifo_ena_reg1;
wire neg_rd_fifo_ena;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
rd_fifo_ena_reg0 <= 1‘b0;
rd_fifo_ena_reg1 <= 1‘b0;
end
else
begin
rd_fifo_ena_reg0 <= rd_fifo_ena;
rd_fifo_ena_reg1 <= rd_fifo_ena_reg0;
end
end
assign neg_rd_fifo_ena = rd_fifo_ena_reg1 & ~rd_fifo_ena_reg0;
reg rd_fifo_req;
reg bps_start;
reg tx_en;
reg[3:0] num;
reg[7:0] tx_data;
reg [3:0] state;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
bps_start <= 1‘b0;
tx_en <= 1‘b0;
tx_data <= 8‘d0;
rd_fifo_req <= 1‘b0;
state <= 4‘b0001;
end
else
case(state)
// 改动
4‘b0001 : //if(rd_fifo_ena_reg1==1‘b0)
if(en_1)
begin
state <= 4‘b0010;
rd_fifo_req <= 1‘b1;
bps_start <= 1‘b1;
tx_en <= 1‘b1;
end
else
begin
state <= 4‘b0001;
rd_fifo_req <= 1‘b0;
bps_start <= 1‘b0;
tx_en <= 1‘b0;
end
4‘b0010 : begin
rd_fifo_req <= 1‘b0;
tx_data <= wr_fifo_data;
state <= 4‘b1000;
end
4‘b1000 : if(num==4‘d10)
begin
bps_start <= 1‘b0;
tx_en <= 1‘b0;
state <= 4‘b0001;
end
else
begin
bps_start <= 1‘b1;
tx_en <= 1‘b1;
state <= 4‘b1000;
end
default : ;
endcase
end
reg rs232_tx_r;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
num <= 4‘d0;
rs232_tx_r <= 1‘b1;
end
else if(tx_en)
begin
if( (clk_bps_reg0 == 1‘b0) && ( clk_bps == 1‘b1 ) ) //clk_bps时钟沿由低位变成高位瞬间
begin
num <= num+1‘b1;
case (num)
4‘d0: rs232_tx_r <= 1‘b0; //???????λ
4‘d1: rs232_tx_r <= tx_data[0]; //????bit0
4‘d2: rs232_tx_r <= tx_data[1]; //????bit1
4‘d3: rs232_tx_r <= tx_data[2]; //????bit2
4‘d4: rs232_tx_r <= tx_data[3]; //????bit3
4‘d5: rs232_tx_r <= tx_data[4]; //????bit4
4‘d6: rs232_tx_r <= tx_data[5]; //????bit5
4‘d7: rs232_tx_r <= tx_data[6]; //????bit6
4‘d8: rs232_tx_r <= tx_data[7]; //????bit7
4‘d9: rs232_tx_r <= 1‘b1; //???????λ
//4‘d10:begin if(en_1==1) num<=0;else num<=10;end
default: rs232_tx_r <= 1‘b1;
endcase
end
else if(num==4‘d10) num <= 4‘d0;
//4‘d10: if(en_1==1) num<=0;else num<=10;end
end
end
assign rs232_tx = rs232_tx_r;
endmodule
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原文地址：http://www.cnblogs.com/w1341787781/p/4604068.html
