串口通信

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module chuankou_1
(
input CLK,rst_n,
input UART_RXD,
output reg UART_TXD,
output reg[19:0] shuju_1

);

reg cnt_1;
reg clk_h;
always @(posedge CLK)
begin
case(cnt_1)
0:
if(b && !a)begin cnt_1=1;end //else cnt_1<=0;

1:
if(count==417) begin clk_h<=!clk_h;end
endcase

end


reg [3:0]state;
reg [30:0] count;
reg [7:0] rx_data;
reg a,b;

reg[1:0]shu_1;
always @ (posedge CLK)
begin
if(x>=‘d20)
x<=0;
if(!rst_n) begin rx_data<=8‘h05;count<=0;end
else begin
case (state)
0:begin en_tx=0;a<=UART_RXD;b<=a; if(b && !a) state<=1;else state<=0;end //当无数据接收完成时关闭，使能，下降沿采样
1:if(count==208) begin if(UART_RXD==0)state<=2;else state<=0;count<=0;end //采集开始位 0电平的中点
else begin state<=1;count<=count+1;end
2:if(count==417) begin state<=3;count<=0;rx_data[0]<=UART_RXD; shuju_1[x]<=UART_RXD;x<=x+1‘b1; end //计数到数据位的中点
else begin state<=2;count<=count+1;end
3:if(count==417) begin state<=4;count<=0;rx_data[1]<=UART_RXD; shuju_1[x]<=UART_RXD;x<=x+1‘b1;; end
else begin state<=3;count<=count+1;end
4:if(count==417) begin state<=5;count<=0;rx_data[2]<=UART_RXD; shuju_1[x]<=UART_RXD;x<=x+1‘b1;; end
else begin state<=4;count<=count+1;end
5:if(count==417) begin state<=6;count<=0;rx_data[3]<=UART_RXD; shuju_1[x]<=UART_RXD;x<=x+1‘b1;; end
else begin state<=5;count<=count+1;end
6:if(count==417) begin state<=7;count<=0;rx_data[4]<=UART_RXD; end
else begin state<=6;count<=count+1;end
7:if(count==417) begin state<=8;count<=0;rx_data[5]<=UART_RXD; end
else begin state<=7;count<=count+1;end
8:if(count==417) begin state<=9;count<=0;rx_data[6]<=UART_RXD; end
else begin state<=8;count<=count+1;end
9:if(count==417) begin state<=10;count<=0;rx_data[7]<=UART_RXD; end
else begin state<=9;count<=count+1;end
10:if(count==417)begin state<=11;count<=0; end //采集结束位
else begin tx_data<=rx_data;en_tx=1;state<=10;count<=count+1; end //提前一个周期就使能发送，解决一起发三个数据返回时，丢掉中间的现象
11:begin tx_data<=rx_data;en_tx=1;state=0;end //获取接收到的数据返回给发送，并且使能发送，回状态一，检测下降沿
default state=0;
endcase
end
end

reg [3:0] state2;
reg [30:0] count2;
reg [7:0] tx_data;
reg en_tx;
always @ (posedge CLK)
begin
if(!rst_n) begin UART_TXD=0;end
else begin

case (state2)
0:if(count2==417) begin state2<=1;count2<=0;end
else begin state2<=0;count2<=count2+1;UART_TXD<=0; end //开始位
1:if(count2==417) begin state2<=2;count2<=0;end
else begin state2<=1;count2<=count2+1;UART_TXD<=tx_data[0];end
2:if(count2==417) begin state2<=3;count2<=0;end
else begin state2<=2;count2<=count2+1;UART_TXD<=tx_data[1];end
3:if(count2==417) begin state2<=4;count2<=0;end
else begin state2<=3;count2<=count2+1;UART_TXD<=tx_data[2];end
4:if(count2==417) begin state2<=5;count2<=0;end
else begin state2<=4;count2<=count2+1;UART_TXD<=tx_data[3];end
5:if(count2==417) begin state2<=6;count2<=0;end
else begin state2<=5;count2<=count2+1;UART_TXD<=tx_data[4];end
6:if(count2==417) begin state2<=7;count2<=0;end
else begin state2<=6;count2<=count2+1;UART_TXD<=tx_data[5];end
7:if(count2==417) begin state2<=8;count2<=0;end
else begin state2<=7;count2<=count2+1;UART_TXD<=tx_data[6];end
8:if(count2==417) begin state2<=9;count2<=0;end
else begin state2<=8;count2<=count2+1;UART_TXD<=tx_data[7];end
9:if(count2==417) begin state2<=10;count2<=0;end
else begin state2<=9;count2<=count2+1;UART_TXD<=1; end //结束位
10:begin if(en_tx==1)state2<=0;else state2<=10;end //发完一次后在这等使能进行发送第二次
default state2<=0;
endcase

end
end

reg[4:0]x;

endmodule

串口通信

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原文地址：http://www.cnblogs.com/w1341787781/p/4604056.html