DSP EPWM学习笔记1 - EPWM定时中断

 75 #include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
 77 
 78 // Select the example to compile in.  Only one example should be set as 1
 79 // the rest should be set as 0.
 80 
 81 #define EXAMPLE1 1  // Basic pinout configuration example
 82 #define EXAMPLE2 0  // Communication pinout example
 83 
 84 #define PWM1_INT_ENABLE  1
 85 #define PWM2_INT_ENABLE  1
 86 #define PWM3_INT_ENABLE  1
 87 
 88 #define PWM1_TIMER_TBPRD   0x1FFF
 89 
 90 
 91 // Prototype statements for functions found within this file.
 92 void Gpio_setup1(void);
 93 void Gpio_setup2(void);
 94 void EpwmGpioInit(void);
 95 void EpwmRegInit(void);
 96 
 97 __interrupt void Epwm1TimerISR(void);
 98 //__interrupt void Epwm2TimerISR(void);
 99 //__interrupt void Epwm3TimerISR(void);
100 
101 uint16_t    EPwm1TimerIntCount = 0;
102 
103 void EpwmRegInit(void)
104 {
105     EALLOW;
106     SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;      // Stop all the TB clocks
107     EDIS;
108 
109     EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // 00 EPWMXSYNC
110 
111 //    EPwm1Regs.TBPRD = 0x1FFF;  //计数周期计算
112 //    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;    // Count up 上升沿计数
113 //    EPwm1Regs.TBCTR = 0;
114 //
115 
116 
117     EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD;
118     EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;    // Count up
119 //    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
120 //    EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE;  // Enable INT
121 //    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 1st event
122 
123     EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
124     EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE;
125     EPwm1Regs.ETPS.bit.INTPRD = ET_2ND;           // Generate INT on 2nd event
126 
127     EALLOW;
128     SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;         // Start all the timers synced
129     EDIS;
130 }
131 
132 void main(void)
133 {
134 // WARNING: Always ensure you call memcpy before running any functions from RAM
135 // InitSysCtrl includes a call to a RAM based function and without a call to
136 // memcpy first, the processor will go "into the weeds"
137    #ifdef _FLASH
138     memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
139    #endif
140 
141 // Step 1. Initialize System Control:
142 // PLL, WatchDog, enable Peripheral Clocks
143 // This example function is found in the f2802x_SysCtrl.c file.
144    InitSysCtrl();
145 
146 // Step 2. Initialize GPIO:
147 // This example function is found in the f2802x_Gpio.c file and
148 // illustrates how to set the GPIO to it‘s default state.
149 // InitGpio(); Skipped for this example
150 
151    EALLOW;
152    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
153    GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
154    GpioDataRegs.GPASET.bit.GPIO0 = 1;        // uncomment if --> Set High initially
155    EDIS;
156 
157 // Step 3. Clear all interrupts and initialize PIE vector table:
158 // Disable CPU interrupts
159    DINT;
160 
161 // Initialize PIE control registers to their default state.
162 // The default state is all PIE interrupts disabled and flags
163 // are cleared.
164 // This function is found in the f2802x_PieCtrl.c file.
165    InitPieCtrl();
166 
167 // Disable CPU interrupts and clear all CPU interrupt flags:
168    IER = 0x0000;
169    IFR = 0x0000;
170 
171 // Initialize the PIE vector table with pointers to the shell Interrupt
172 // Service Routines (ISR).
173 // This will populate the entire table, even if the interrupt
174 // is not used in this example.  This is useful for debug purposes.
175 // The shell ISR routines are found in f2802x_DefaultIsr.c.
176 // This function is found in f2802x_PieVect.c.
177    InitPieVectTable();
178 
179 // Step 4. Initialize all the Device Peripherals:
180 // Not required for this example
181 
182 //   EpwmGpioInit(); 因为仅仅使用epwm的定时器功能，所以不需要初始化外设
183    EpwmRegInit();
184 
185    EALLOW;
186    PieVectTable.EPWM1_INT = &Epwm1TimerISR;
187 //   PieVectTable.EPWM2_INT = &Epwm2TimerISR;
188 //   PieVectTable.EPWM3_INT = &Epwm3TimerISR;
189    EDIS;
190 
191    IER |= M_INT3;
192 
193    PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE;
194 //   PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE;
195 //   PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE;
196 
197    EINT;
198    ERTM;
199 
200 // Step 5. User specific code:
201    while(1);
202 }
203 
204 __interrupt void Epwm1TimerISR(void)
205 {
206     EPwm1Regs.ETCLR.bit.INT = 1;
207     EPwm1TimerIntCount++;
208 
209     if(EPwm1TimerIntCount > 5000)
210     {
211         EPwm1TimerIntCount = 0;
212         GpioDataRegs.GPATOGGLE.bit.GPIO0 = 1;
213     }
214 
215     PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
216 }
217 
218 void Gpio_setup1(void)
219 {
220    // Example 1:
221    // Basic Pinout.
222    // This basic pinout includes:
223    // PWM1-3, TZ1-TZ4, SPI-A, EQEP1, SCI-A, I2C
224    // and a number of I/O pins
225 
226    // These can be combined into single statements for improved
227    // code efficiency.
228 
229    // Enable PWM1-3 on GPIO0-GPIO5
230    EALLOW;
231    GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;   // Enable pullup on GPIO0
232    GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;   // Enable pullup on GPIO1
233    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;   // Enable pullup on GPIO2
234    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;   // Enable pullup on GPIO3
235    GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;   // Enable pullup on GPIO4
236    GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;   // Enable pullup on GPIO5
237    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;  // GPIO0 = PWM1A
238    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;  // GPIO1 = PWM1B
239    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;  // GPIO2 = PWM2A
240    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;  // GPIO3 = PWM2B
241    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;  // GPIO4 = PWM3A
242    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;  // GPIO5 = PWM3B
243 
244    // Enable an GPIO output on GPIO6&7, set it high
245    GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;   // Enable pullup on GPIO6
246    GpioDataRegs.GPASET.bit.GPIO6 = 1;   // Load output latch
247    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0;  // GPIO6 = GPIO6
248    GpioCtrlRegs.GPADIR.bit.GPIO6 = 1;   // GPIO6 = output
249 
250    GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0;   // Enable pullup on GPIO7
251    GpioDataRegs.GPASET.bit.GPIO7 = 1;   // Load output latch
252    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0;  // GPIO7 = GPIO7
253    GpioCtrlRegs.GPADIR.bit.GPIO7 = 1;   // GPIO7 = output
254 
255    // Enable Trip Zone input on GPIO12
256    GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;   // Enable pullup on GPIO12
257    GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input
258    GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1;  // GPIO12 = TZ1
259 
260    // Enable SPI-A on GPIO16 - GPIO19
261    GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pullup on GPIO16
262    GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pullup on GPIO17
263    GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;   // Enable pullup on GPIO18
264    GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;   // Enable pullup on GPIO19
265    GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input
266    GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input
267    GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input
268    GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input
269    GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1;  // GPIO16 = SPICLKA
270    GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1;  // GPIO17 = SPIS0MIA
271    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1;  // GPIO18 = SPICLKA
272    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1;  // GPIO19 = SPISTEA
273 
274    // Enable SCI-A on GPIO28 - GPIO29
275    GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;   // Enable pullup on GPIO28
276    GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input
277    GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;  // GPIO28 = SCIRXDA
278    GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;   // Enable pullup on GPIO29
279    GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;  // GPIO29 = SCITXDA
280 
281    // Make GPIO34 an input
282    GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0;  // Enable pullup on GPIO34
283    GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34
284    GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0;  // GPIO34 = input
285    EDIS;
286 }
287 
288 void Gpio_setup2(void)
289 {
290    // Example 1:
291    // Communications Pinout.
292    // This basic communications pinout includes:
293    // PWM1-3, SPI-A, SCI-A
294    // and a number of I/O pins
295 
296    // Enable PWM1-3 on GPIO0-GPIO5
297    EALLOW;
298    GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;   // Enable pullup on GPIO0
299    GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;   // Enable pullup on GPIO1
300    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;   // Enable pullup on GPIO2
301    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;   // Enable pullup on GPIO3
302    GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;   // Enable pullup on GPIO4
303    GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;   // Enable pullup on GPIO5
304    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;  // GPIO0 = PWM1A
305    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;  // GPIO1 = PWM1B
306    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;  // GPIO2 = PWM2A
307    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;  // GPIO3 = PWM2B
308    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;  // GPIO4 = PWM3A
309    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;  // GPIO5 = PWM3B
310 
311    // Enable an GPIO output on GPIO6&7
312    GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;   // Enable pullup on GPIO6
313    GpioDataRegs.GPASET.bit.GPIO6 = 1;   // Load output latch
314    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0;  // GPIO6 = GPIO6
315    GpioCtrlRegs.GPADIR.bit.GPIO6 = 1;   // GPIO6 = output
316 
317    GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0;   // Enable pullup on GPIO7
318    GpioDataRegs.GPASET.bit.GPIO7 = 1;   // Load output latch
319    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0;  // GPIO7 = GPIO7
320    GpioCtrlRegs.GPADIR.bit.GPIO7 = 1;   // GPIO7 = output
321 
322    // Enable SPI-A on GPIO16 - GPIO19
323    GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pullup on GPIO16 (SPICLKA)
324    GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pullup on GPIO17 (SPIS0MIA)
325    GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;   // Enable pullup on GPIO18 (SPICLKA)
326    GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;   // Enable pullup on GPIO19 (SPISTEA)
327    GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input
328    GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input
329    GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input
330    GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input
331    GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1;  // GPIO16 = SPICLKA
332    GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1;  // GPIO17 = SPIS0MIA
333    GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1;  // GPIO18 = SPICLKA
334    GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1;  // GPIO19 = SPISTEA
335 
336    // Enable SCI-A on GPIO28 - GPIO29
337    GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;   // Enable pullup on GPIO28
338    GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // asynch input
339    GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;  // GPIO28 = SCIRXDA
340    GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;   // Enable pullup on GPIO29
341    GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;  // GPIO29 = SCITXDA
342 
343    // Enable CAN-A on GPIO30 - GPIO31
344    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;   // Enable pullup on GPIO30
345    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;  // GPIO30 = CANTXA
346    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;   // Enable pullup on GPIO31
347    GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // asynch input
348    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;  // GPIO31 = CANRXA
349 
350 /* Applicable only on those packages with GPIO32 and GPIO33 pinned out
351    // Enable I2C-A on GPIO32 - GPIO33
352    GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;   // Enable pullup on GPIO32
353    GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;   // Enable pullup on GPIO33
354    GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input
355    GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input
356    GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1;  // GPIO32 = SDAA
357    GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1;  // GPIO33 = SCLA
358 */
359    // Make GPIO34 an input
360    GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0;   // Enable pullup on GPIO34
361    GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;  // GPIO34 = GPIO34
362    GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0;   // GPIO34 = input
363 
364    EDIS;
365 }
366 
367 //===========================================================================
368 // No more.
369 //===========================================================================