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将a Latch一级
wire a; reg en; always @ (posedge clk) en = a; reg [3:0] cnt; always @ (posedge clk or posedge rst) if (rst) cnt <= 4’d0; else if (en) cnt <= cnt + 4’d1;
wire a; reg en; always @ (posedge clk) en <= a; reg [3:0] cnt; always @ (posedge clk or posedge rst) if (rst) cnt <= 4’d0; else if (en) cnt <= cnt + 4’d1;
结论：如果信号想要用clk敲出来，一定要用<=，如果用=敲出来可能会有意想不到的结果（至少仿真是这样的。）
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原文地址：http://www.cnblogs.com/myfudream/p/4672736.html
