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Verilog之event

时间:2015-07-28 21:00:23      阅读:132      评论:0      收藏:0      [点我收藏+]

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1  Explicit event

  The value changes on nets and variable can be used as events to trigger the execution of a statement. 

  The event can also be based on the direction of the change that is, towards the value 1 ( posedge) or towards the value 0 (negedge).

  - A negedge shall be detected on the transition from 1 to x, z, or 0, and from x or z to 0

  - A posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1    

@(trig or enable) rega = regb;  // event "or" is the same as ","
@(trig, enable) rega = regb;

@(posedge clk_a or posedge ck_b or trig) rega = regb;

always @(a, b, c, d, e)
always @(posedge clk, negedge rstn)
always @(a or b, c, d or e)

 

2  Implicit event

// Example 1
    always @(*)    // equivalent to @(a or b or c or d or f)
        y = (a & b) | (c & d) | myfunction(f);

// Example 2
    always @*    begin  // equivalent to @(a or b or c or d or tmp1 or tmp2)
        tmp1 = a & b;
        tmp2 = c & d;
        y = tmp1 | tmp2;
    end

// Example 3
    always @*    begin    // equivalent to @(b)
        @(i) kid = b;    // i is not added to @*
    end

// Example 4
    always @*    begin    // equivalent to @(a, b, c, d)
        x = a ^ b;
        @*
            x = c  ^ d;
    end

 

  

Verilog之event

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原文地址:http://www.cnblogs.com/mengdie/p/4684144.html

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