基于verilog的分频器设计（半整数分频，小数分频：下）

module fenpin(clk,rst_n,clk_out);
input clk;
input rst_n;
output clk_out;
reg clk_out2;
wire clk_out1;
reg [1:0] cnt;
reg FB_CLK;
always@(posedge clk_out2,negedge rst_n)
begin if (!rst_n)
FB_CLK<=0;
else
FB_CLK<=~FB_CLK;
end
always@(posedge clk_out1,negedge rst_n)
begin if (!rst_n)
begin
cnt<=0;
clk_out2<=0;
end
else if (cnt==2)
begin
cnt<=0;
clk_out2<=1;
end
else
begin
cnt<=cnt+1‘b1;
clk_out2<=0;
end
end
xor xor1(clk_out1,clk,FB_CLK);
wire CLK_OUT_R;
assign CLK_OUT_R=(cnt==1) ? 1‘b0:1‘b1;
assign clk_out=clk_out2 | CLK_OUT_R;
endmodule